Description

You will perform functional verification for GPU subsystems, including Shader, Texture, and Memory systems.

Responsibilities

• Develop scalable SystemVerilog/UVM testbenches for unit and cluster level verification.
• Debug functional errors in RTL models using simulation and debug tools.
• Define, maintain, and execute verification testplans to drive coverage to closure.
• Triage regression failures, update testbenches, and maintain regression status.
• Review architecture and micro-architecture specifications alongside architects and RTL designers.

Required Skills

• 5+ years of industry experience in a design verification role.
• Proficiency in SystemVerilog, UVM, OVM, and OOP/C++.
• Experience creating, running, and debugging SystemVerilog/UVM constraint-random testbenches.
• Strong knowledge of code coverage and functional coverage driven verification methodologies.
• Working knowledge of scripting languages such as Python or Perl.
• Understanding of micro-architecture, logic design, FSMs, and arithmetic datapath pipelines.
• Solid programming skills with a grasp of algorithms and data structures.
• Experience with RTL design and debugging.

Preferred Skills

• Knowledge of GPU architectures, specifically Shader, Texture, or Memory systems.

Key Skills

Education

Any Graduate