Description

You will focus on gate-level simulations and verification flow optimization.

Responsibilities

• Execute gate-level simulations (GLS) and manage testbench updates for these runs.
• Perform 0-delay and post-layout simulations using SDF back-annotations for Best, Typical, and Worst Case analysis.
• Optimize verification flows using Grey/Black-boxing techniques.
• Communicate technical requirements and issues with Implementation, PnR, and Design teams.
• Maintain project documentation and version control using Confluence, Git, and Jira.

Required Skills

• 5+ years of experience in Design Verification.
• Extensive experience with gate-level simulation (GLS).
• Proficiency in Perl or Python scripting.
• Experience with Make, YAML, and JSON file systems.
• Understanding of RTL synthesis, Static Timing Analysis (STA), and LEC flows.
• Hands-on experience with Git, Jira, and Confluence.
• Ability to work with SDF back-annotations.

Education

• Any Graduate degree.

Key Skills

Education

Any Graduate