Description

You will own gate-level simulation execution and verification flow optimization for physical design sign-off.

This role is on-site.

Responsibilities

• Execute gate-level simulations (GLS) and manage testbench updates for regression runs.
• Perform 0-delay and post-layout simulations using SDF back-annotations for Best, Typical, and Worst Case analysis.
• Optimize verification flows using Grey/Black-boxing techniques to improve coverage and runtime.
• Communicate technical requirements and verification issues with Implementation, PnR, and Design teams.
• Maintain project documentation and version control using Confluence, Git, and Jira.

Required Skills

• 5+ years of experience in Design Verification.
• Extensive hands-on experience with gate-level simulation (GLS).
• Proficiency in Perl or Python scripting for automation.
• Experience with Make, YAML, and JSON file systems for build and configuration management.
• Understanding of RTL synthesis, Static Timing Analysis (STA), and LEC flows.
• Ability to work with SDF back-annotations for timing-aware simulations.
• Hands-on experience with Git, Jira, and Confluence.

Key Skills

Education

Any Graduate