Description

You will architect and build verification environments for IPs and SoCs featuring embedded CPUs and analog mixed-signal interfaces.

Responsibilities

• Architect and create verification environments using SystemVerilog and UVM.
• Develop comprehensive test plans and coverage metrics based on technical specifications.
• Write and execute block-level and chip-level tests.

Required Skills

• 5+ years of experience in design verification.
• Expertise in SystemVerilog and Universal Verification Methodology (UVM).
• Proficiency with Synopsys or Cadence EDA verification tools.
• Experience verifying SoCs with embedded CPUs.
• Experience with analog mixed-signal interfaces.
• Knowledge of embedded systems.
• Ability to derive coverage metrics from specifications.

Key Skills

Education

Any Gradute