Description

You will architect and develop complex verification environments for digital designs.

Responsibilities

• Build and maintain verification environments using SystemVerilog.
• Write and manage automation scripts in Perl and Ruby.
• Utilize Makefiles for build and test orchestration.
• Apply formal verification techniques and functional verification tools.
• Collaborate on RTL design understanding and software development tasks.

Required Skills

• 5+ years of experience in design verification.
• Proficiency in SystemVerilog for verification environments.
• Strong scripting skills in Perl and Ruby.
• Experience with Make or similar build tools.
• Familiarity with formal tools and functional verification environments.
• Understanding of computer organization and architecture.
• Experience using VCS, Cadence, or Mentor Graphics tools.

Preferred Skills

• Background in software development practices.
• Exposure to RTL design processes.

Key Skills

Education

Any Gradute