Description

Architect and build verification environments for IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.

Responsibilities

• Architect verification environments using SystemVerilog and UVM for IPs and SoCs.
• Develop test plans and coverage metrics based on specifications to write block and chip-level tests.
• Automate environment creation, test generation, and debugging using Perl or Python scripts.
• Perform failure analysis on RTL and Gate simulations and resolve issues with design engineers.
• Create low power testcases using UPF or CPF to verify SoC power intent.

Required Skills

• 7+ years of experience in pre-silicon design verification.
• Proficiency in Verilog-HDL, SystemVerilog, and UVM/OVM.
• Experience with SoC verification using ARM Cortex Microcontrollers.
• Strong knowledge of SV Assertions and functional code coverage.
• Experience verifying peripheral bus VIPs including GPIO, UART, SPI, SW, JTAG, and I2C.
• Proficiency with Cadence tools including NCVerilog, NCSIM, and Simvision.
• Experience with SDF annotated simulations and understanding of parasitic delays and timings.
• Proficiency in C-shell scripting, Python, C, or C++.

Preferred Skills

• Experience with linting tools such as Spyglass.
• Exposure to FPGA programming and FPGA tools.

Key Skills

Education

Any Graduate