Description

You will drive the verification process for IP, sub-systems, and SoCs to ensure high design quality.

This role is on-site.

Responsibilities

• Define and implement IP/SoC verification plans and build test benches for IP and sub-system level verification.
• Develop functional tests based on the verification test plan and drive closure using functional and code coverage metrics.
• Debug, root-cause, and resolve functional failures in collaboration with the Design team.
• Partner with cross-functional teams including Design, Model, Emulation, and Silicon validation.
• Drive continuous improvements to verification methodologies, tools, and technologies.

Required Skills

• 7+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• 7+ years of experience in IP/sub-system and/or SoC level verification using SystemVerilog, UVM, or OVM.
• Proven track record of first-pass success in ASIC development cycles.
• Experience architecting and implementing Design Verification infrastructure and executing the full verification cycle.
• Proficiency with EDA tools and scripting in Python, TCL, Perl, or Shell.
• Strong debugging skills to resolve complex functional failures.
• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.

Preferred Skills

• Experience developing UVM-based verification environments from scratch.
• Experience verifying GPU/CPU designs or ARM/RISC-V based sub-systems/SoCs.
• Experience with high-speed interface verification such as PCIe, RoCE, DDR, HBM, or Ethernet.

Key Skills

Education

Any Graduate