Description

You will develop and manage verification environments for RTL and Gate Level Netlist designs.

This role is remote.

Responsibilities

• Develop test benches using SystemVerilog and UVM for RTL and Gate Level Netlist designs.
• Create and integrate C tests and Application Programming Interfaces (APIs).
• Execute test development and debug for functionality, power, performance, error, and connectivity.
• Implement continuous integration and regression testing for simulation at both RTL and Gate Level.
• Drive functional and code coverage improvements through targeted test development.

Required Skills

• 5+ years of experience in Design Verification Engineering.
• Proficiency in SystemVerilog and Universal Verification Methodology (UVM).
• Experience writing tests in Python and C.
• Hands-on experience with software build flows and API integration.
• Knowledge of RTL and Gate Level Netlist Design Under Test (DUT).
• Experience with Unified Power Format (UPF) for power-aware verification.

Preferred Skills

• Ability to manage test development, integration, and debugging.

Key Skills

Education

Any Graduate