Description

You will focus on Gate Level Simulation (GLS) and verification flow optimization.

Responsibilities

• Execute GLS work including 0-delay simulations and post-layout simulations with SDF back annotations for Best, Typical, and Worst Case analysis.
• Update testbenches specifically for GLS requirements.
• Optimize verification flows using Grey/Black-boxing techniques.
• Communicate technical requirements and issues with Implementation, PnR, and Design teams.
• Document processes in Confluence and manage tasks via JIRA.

Required Skills

• 5+ years of experience in Design Verification.
• Deep expertise in Gate Level Simulation (GLS).
• Proficiency in scripting with Perl or Python.
• Experience with Make, YAML, and JSON file systems.
• Working knowledge of RTL synthesis, Static Timing Analysis, and LEC flows.
• Proficiency with Git version control.
• Ability to handle SDF back annotations.
• Any Graduate degree.

Preferred Skills

• Experience with JIRA and Confluence for project execution and documentation.

Key Skills

Education

Any Graduate