Description

You will own gate-level simulation and verification flow optimization for complex designs.

This role is remote.

Responsibilities

• Execute major gate-level simulation work, including testbench updates.
• Perform 0-delay and post-layout simulations with SDF back-annotations for Best, Typical, and Worst Case analysis.
• Optimize verification flows using Grey and Black-boxing techniques.
• Communicate technical requirements and issues with Implementation, PnR, and Design teams.
• Manage project execution and documentation using JIRA, Confluence, and GIT.

Required Skills

• 8+ years of experience in Design Verification.
• Expertise in Perl or Python scripting.
• Experience with Make, YAML, and JSON file systems.
• Strong understanding of RTL synthesis, Static Timing Analysis, and LEC flows.
• Proficiency with GIT version control and JIRA project management.
• Hands-on experience with PnR workflows.
• Ability to work with Confluence for technical documentation.

Preferred Skills

• Any Graduate degree.

Key Skills

Education

Any Graduate