Description

You will own the end-to-end design verification process for RTL and Gate Level Netlist designs.

Responsibilities

• Develop and maintain testbenches using SystemVerilog and UVM.
• Integrate C tests, APIs, and software build flows into the verification environment.
• Execute test development and debug for functionality, power, performance, error, and connectivity.
• Manage continuous integration and regression testing setups for simulation.
• Drive coverage collection and closure to meet design requirements.

Required Skills

• 5+ years of experience in Design Verification Engineering.
• Proficiency in SystemVerilog and Universal Verification Methodology (UVM).
• Strong Python coding skills for verification tasks.
• Experience with C tests and API integration.
• Knowledge of Unified Power Format (UPF) for power-aware simulation and emulation.
• Experience with XProp simulation and regression.
• Ability to perform verification at both RTL and Gate Level Netlist.

Preferred Skills

• Proven track record in testbench creation and maintenance.

Key Skills

Education

Any Graduate