Description

You will own the verification of digital designs using industry-standard methodologies.

This role is on-site.

Responsibilities

• Develop and execute verification plans for digital blocks.
• Write and debug Verilog/SystemVerilog testbenches.
• Implement UVM-based verification environments.
• Analyze simulation results and debug design issues.
• Collaborate with design teams to ensure sign-off.

Required Skills

• 5+ years of experience in digital design verification.
• Strong understanding of digital design fundamentals.
• Proficiency in Verilog and SystemVerilog.
• Basic knowledge of UVM methodology.
• Experience with simulation tools and debug techniques.
• Any Graduate degree in Engineering or related field.

Key Skills

Education

Any Graduate