Description

Lead end-to-end ASIC verification projects, managing technical delivery, client communications, and team mentorship.

Responsibilities

• Own complete verification cycles, including test plan development, component integration, and coverage closure.
• Execute gate-level simulations (GLS), including netlist setup and timing debug with SDF.
• Manage project scope, estimation, scheduling, and deliverables to ensure customer acceptance.
• Direct team members through technical reviews, coaching, and career guidance.
• Oversee resource and tool compatibility to ensure successful project delivery.

Required Skills

• 8+ years of professional experience in ASIC verification.
• 3+ years of experience with SystemVerilog HVL.
• 2+ years of experience with UVM.
• Proven experience leading teams of 5+ members as a Technical Lead.
• Hands-on experience executing multiple SoC verification projects.
• Experience with Low-Power and UPF flows.
• Proficiency in Netlist (GLS) setup and extensive debug with timing simulations.
• Knowledge of industry standard protocols such as Ethernet, MIPMI, ARM Processors, or AXI/AHB.
• Scripting proficiency in Make, Perl, or Python.

Preferred Skills

• Experience in stress and corner testing, assertions, and failure debug.

Key Skills

Education

Any Graduate