Description

Lead verification projects through hands-on execution, technical reviews, and team management.

This role is on-site.

Responsibilities

• Lead verification projects from test plan development through to coverage closure and customer acceptance.
• Manage team members through coaching, mentoring, and career planning.
• Define project scope, estimation, schedules, and deliverables.
• Develop and integrate BFM, driver, monitor, and scoreboard components into test benches.
• Execute gate-level simulations (GLS) and perform extensive debug with timing (SDF) simulations.

Required Skills

• 10+ years of total experience with at least 1+ year as a Technical Lead managing teams of 5+.
• 3+ years of experience in SystemVerilog HVL.
• 2+ years of experience in UVM.
• Proven experience executing SoC verification projects.
• Experience with Netlist (GLS) setup and timing (SDF) simulations.
• 1+ year of experience with Low-Power and UPF flows.
• Proficiency in Make, Perl, or Python for management.
• Knowledge of industry standard protocols such as Ethernet, MIPI, ARM Processors, or AXI/AHB.
• Ability to handle stress testing, corner testing, failure debug, assertions, and coverage closure.

Preferred Skills

• Experience with Application-Specific Integrated Circuits (ASIC) design flows.
• Background in Computer Simulations for complex System on a Chip (SoC) architectures.
• Familiarity with Unified Power Format (UPF) for low-power verification strategies.

Key Skills

Education

Any Graduate