Description

Job Description – DFT Engineers (4–10 Years) | Permanent | Bangalore

We are hiring DFT Engineers across multiple levels for a long-term, permanent opportunity in Bangalore.
Candidates must have strong experience in DFT – Scan, ATPG, MBIST, IJTAG, Hard IP Testing, and Repair Flows.

🔹 DFT Engineer (4–6 Years)

1. Scan Insertion & ATP

Scan insertion, test point insertion, DFT rule checks.

ATP pattern generation & basic pattern debug.

2. MBIST & IJTAG

MBIST implementation and verification.

IJTAG (IEEE 1687) network development and pattern validation.

3. Hard IP & JTAG

DFT support for Hard IP integration.

JTAG design, validation, and boundary scan basics.

🔹 Senior DFT Engineer (6–8 Years)

1. Scan & ATPG

Scan architecture, compression, ATPG pattern generation.

Coverage analysis and debug of complex test issues.

2. MBIST & BIST (Clocking)

MBIST planning, insertion, and validation.

Logic BIST implementation with clocking structures.

3. Hard IP & Boundary Scan

Hard IP test planning and DFT integration.

Boundary scan (1149.1/1149.6) architecture and validation.

🔹 Lead DFT Engineer (8–10 Years)

1. Scan & ATPG

End-to-end DFT strategy for scan & ATPG flows.

Lead full-chip ATPG signoff and pattern bring-up.

2. MBIST & Repair Flow

MBIST ownership, redundancy analysis, and repair flow implementation.

Fuse flow and silicon bring-up support.

3. JTAG & Hard IP Testing

JTAG architecture ownership and test strategy.

Hard IP DFT planning, integration, and validation leadership.

📍 Location: Bangalore

📝 Type: Permanent | Long-term

Key Skills

Education

Graduation