Description

Own the design-for-test strategy and implementation for complex semiconductor products.

Responsibilities

• Execute scan insertion, test point insertion, and DFT rule checks.
• Generate ATPG patterns and debug complex test issues.
• Implement and verify MBIST structures, including logic BIST and clocking.
• Develop IJTAG (IEEE 1687) networks and validate boundary scan flows.
• Lead hard IP DFT integration and repair flow implementation.

Required Skills

• 4–10 years of experience in DFT engineering.
• Strong proficiency in Scan insertion and ATPG pattern generation.
• Hands-on experience with MBIST implementation and validation.
• Knowledge of IJTAG (IEEE 1687) and JTAG design.
• Experience with Hard IP testing and boundary scan (1149.1/1149.6).
• Ability to implement repair flows, redundancy analysis, and fuse flows.
• Graduation degree in Engineering or related field.

Preferred Skills

• Experience with automotive DFT requirements.
• Background in full-chip ATPG signoff and silicon bring-up.

Key Skills

Education

Graduation