Description

You will own the development and implementation of DFT strategies for ASIC designs, integrating testability features with design and verification teams.

This role is on-site.

Responsibilities

• Implement scan insertion, ATPG, and Built-In Self-Test (BIST) architectures.
• Apply JTAG and boundary scan techniques to ensure design testability.
• Debug and resolve DFT-related issues during design and testing phases.
• Document DFT methodologies and provide technical reports to the design team.

Required Skills

• 4 to 12 years of experience in Design for Test (DFT).
• Proficiency in Verilog and VHDL.
• Hands-on experience with Scan Insertion and ATPG.
• Expertise with JTAG and BIST.
• Experience using Cadence Modus/Xcelium.
• Experience using Synopsys DFTMAX/TetraMax.
• Knowledge of Mentor Graphics Tessent.

Key Skills

Education

Any Graduate