Description

Key Skills: DFT Design, Scan Insertion, JTAG, System Verilog, UVM, ATPG, MBIST

Roles & Responsibilities:

• Implement hardware Memory BIST (MBIST) features supporting ATE and in-system testing.
• Collaborate with design, verification, and backend teams for seamless integration of test logic.
• Design and debug test solutions independently with minimal supervision.
• Ensure high-quality pattern generation and release for production testing.
• Support silicon bring-up, characterization, and yield improvement activities.
• Develop automation scripts using Python or Perl to improve testing efficiency.
• Perform post-silicon validation and debugging using ATE patterns.
• Conduct verification using System Verilog and validate design test timing.
• Execute gate-level simulations and debug using VCS or equivalent simulators.
• Stay updated with latest trends in memory testing and silicon validation.
• Work closely with cross-functional teams to resolve silicon and test issues.

Experience Required:

• 9-13 years of experience in DFT, MBIST, and semiconductor test methodologies.
• Strong hands-on experience in scan insertion, JTAG implementation, and test pattern validation.
• Experience working with ATE environments and production test flows.
• Good knowledge of System Verilog, UVM, and verification methodologies.
• Experience in gate-level simulation, timing validation, and debugging.
• Exposure to post-silicon validation and yield improvement processes.
• Experience working with cross-functional teams in full chip lifecycle.
• Strong scripting skills in Python, Perl, or similar automation tools.

Education: Any Graduation

Key Skills

Education

Any Graduate