Description

You will own scan insertion, ATPG pattern generation, and gate-level verification for semiconductor designs.

This role is on-site.

Responsibilities

• Perform scan insertion and debug SCAN DRC/coverage issues.
• Generate ATPG patterns for test coverage.
• Execute gate level simulations, including zero delay and timing delay simulations.
• Implement and work with JTAG/P1500 protocols.

Required Skills

• 3+ years of experience in DFT engineering.
• Hands-on experience with scan insertion and coverage debug.
• Proficiency in ATPG pattern generation.
• Experience conducting gate level simulations (Zero delay/Timing Delay).
• Knowledge of JTAG/P1500 protocols.
• Ability to write scripts using Perl or Tcl.
• Any Graduate degree.

Preferred Skills

• Knowledge of timing, formal verification, or PD flow.

Key Skills

Education

Any Graduate