Description

Key Skills: DFT, ATPG, MBIST, Scan Insertion, Boundary Scan, JTAG, Python, Perl, TCL, Silicon Debug

Good to Have Skills: Experience with SoC/ASIC designs, advanced process nodes, ATE (Automatic Test Equipment), yield analysis, microcontroller DFT methodology, test pattern validation, and cross-functional collaboration with RTL design, verification, and physical implementation teams.

Roles & Responsibilities:

• Define and implement DFT methodologies for SoCs, MCUs, or test chips to ensure manufacturability and reliability.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level for comprehensive test coverage.
• Architect innovative DFT techniques for advanced process nodes to meet industry standards.
• Generate ATPG patterns for stuck-at, transition, and path delay faults with highest coverage.
• Debug test pattern issues during silicon bring-up and ensure stability on ATE equipment.
• Work closely with RTL design, verification, physical implementation, and test engineering teams for successful project delivery.
• Support silicon characterization and yield improvement activities to optimize manufacturing outcomes.
• Contribute to overall microcontroller or SoC DFT methodology development and standardization.

Experience Required: Typically 5-8 years in DFT for complex SoCs/ASICs with hands-on experience in debugging silicon test issues and yield analysis.

Education: Bachelor's/Master's in Electrical Engineering, Microelectronics, or related field

Key Skills

Education

Any Graduate