Description

You will define and implement DFT methodologies for SoCs and MCUs to ensure manufacturability and reliability.

This role is on-site.

Responsibilities

• Insert scan chains, boundary scan, MBIST, and repair logic at the RTL or gate level.
• Generate ATPG patterns for stuck-at, transition, and path delay faults to maximize coverage.
• Debug test pattern issues during silicon bring-up and ensure stability on ATE equipment.
• Support silicon characterization and yield analysis to optimize manufacturing outcomes.
• Collaborate with RTL design, verification, and physical implementation teams.

Required Skills

• 5+ years of experience in DFT for complex SoCs or ASICs.
• Hands-on expertise with DFT, ATPG, MBIST, Scan Insertion, and Boundary Scan.
• Proficiency in JTAG and silicon debug methodologies.
• Scripting skills in Python, Perl, and TCL.
• Experience with advanced process nodes and microcontroller DFT.
• Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related field.

Key Skills

Education

Any Graduate