Description

You will own the complete DFT lifecycle from initial specification to final pattern delivery for sub-systems and SoCs.

This role is on-site.

Responsibilities

• Write SoC specifications including functional and timing descriptions for interfaces, registers, state machines, and power domains.
• Perform top and block-level DFT insertion, including scan compression, boundary scan, JTAG, IEEE 1500 wrappers, MBIST, LBIST, and ATPG.
• Verify DFT circuitry, debug timing simulation issues, and validate timing constraints with physical design teams.
• Define SoC level constraints and partitions for RTL designers, floorplan engineers, and PD teams.
• Collaborate with synthesis, STA, and PD teams to meet PPA targets and diagnostic test coverage goals.

Required Skills

• 8+ years of industry experience in semiconductor design.
• 3+ years of hands-on experience with DFT and test flows for large, complex SoCs using Synopsys or Mentor EDA tools.
• Proficiency in System Verilog and VHDL.
• Strong knowledge of JTAG, ATPG, scan compression, IEEE 1500 Std, MBIST, and LBIST.
• Experience with Synopsys DFT Compiler, Tetramax, and VCS.
• Experience in RTL simulation, synthesis, Linting, CDC checks, STA, and DFT quality metrics.
• Hands-on expertise in Perl, Tcl, and Unix scripting.
• Ability to model complex state machines, data-paths, and high-speed bus protocols such as PCIe.
• Experience defining system architecture, register definitions, and memory organization.

Preferred Skills

• Experience with TestKompress, Tessent, or Modus/Encounter tool suites.

Key Skills

Education

Bachelor's Degree