Description

You will drive the Design for Testability strategy and execution for complex ASIC/SoC designs.

Responsibilities

• Lead DFT planning, architecture, and implementation for ASIC/SoC designs.
• Define and implement DFT methodologies including Scan, JTAG, ATPG, and MBIST.
• Own DFT signoff, including coverage analysis and pattern generation.
• Review RTL for testability and provide DFT guidelines to design teams.
• Mentor and manage a DFT team and ensure delivery quality.

Required Skills

• 7+ years of experience in DFT for ASIC/SoC.
• Strong hands-on experience in DFT, ATPG, Scan, JTAG, and MBIST.
• Strong RTL understanding.
• Experience leading a team for a minimum of 2 years.
• Good knowledge of DFT flows and industry best practices.
• 7 to 15 years of working experience.

Key Skills

Education

Not specified