Description

You will drive the Design for Testability strategy and execution for complex ASIC/SoC designs.

This role is on-site.

Responsibilities

• Lead DFT planning, architecture, and implementation for ASIC/SoC designs.
• Define and implement DFT methodologies including Scan, JTAG, ATPG, and MBIST.
• Own DFT signoff, including coverage analysis and pattern generation.
• Review RTL for testability and provide DFT guidelines to design teams.
• Mentor and manage a DFT team to ensure delivery quality.

Required Skills

• 7 to 15 years of experience in DFT for ASIC/SoC.
• Strong hands-on experience with DFT, ATPG, Scan, JTAG, and MBIST.
• Deep understanding of RTL design and testability.
• Experience leading a team for a minimum of 2 years.
• Good knowledge of DFT flows and industry best practices.
• Proven track record in DFT methodology implementation.

Preferred Skills

• Experience with complex SoC integration challenges.
• Advanced knowledge of coverage closure techniques.

Key Skills

Education

Not specified