Description

You will lead DFT efforts across the full silicon lifecycle, from logic integration to post-silicon debug.

Responsibilities

• Execute DFT logic integration and verification covering SCAN, ATPG, MBIST, and Boundary Scan.
• Manage pattern generation, verification, and delivery to the ATE team.
• Perform gate-level ATPG simulations with and without timing constraints.
• Debug low coverage issues and Design Rule Checking (DRC) fixes.
• Lead junior engineers through mentoring, training, and project leadership.

Required Skills

• 10+ years of experience in all aspects of DFT.
• Expertise in Automatic Test Pattern Generation (ATPG).
• Proficiency with Boundary Scan and MBIST.
• Experience with Synopsys TestMAX tools.
• Strong debugging skills for DRC and coverage issues.
• Ability to perform post-silicon debug and support failing patterns.
• Proficiency in Perl or Tcl for flow automation.
• Background in computer simulations.
• Proven leadership and customer interaction capabilities.

Preferred Skills

• Experience in developing and automating complex DFT flows.

Key Skills

Education

Any Graduate