Description

You will develop and execute verification strategies for DFX features, focusing on DFT aspects such as Scan, BIST, and JTAG protocols.

Responsibilities

• Develop and execute verification strategies for DFX features including Scan, Built-In Self-Test (BIST), and JTAG protocols.
• Collaborate with design and product engineering teams to deliver manufacturing test patterns and integrate DFX features.
• Verify and debug complex systems using Verilog.
• Conduct gate-level simulations (GLS) and develop patterns for silicon debug.

Required Skills

• 3+ years of practical experience in digital ASIC verification.
• Strong understanding of ARM CoreSight architecture and implementation.
• Proficiency in Verilog and SystemVerilog.
• Experience with JTAG IEEE-1149.1 and IJTAG IEEE P1687 standards.
• Ability to use Perl, Python, Tcl Scripts, Makefile, or C++.
• Familiarity with Synopsys Verdi for debugging.
• Bachelor's or Master's degree in Electrical Engineering or a related field.

Key Skills

Education

Bachelor's or Master's degree