Description

You will focus on digital architecture, design, and verification for ASIC and SoC environments.

Responsibilities

• Drive top-level microarchitecture definition and develop necessary RTL.
• Manage chip-level integration, verification plan development, and verification.
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
• Support test program development, chip validation, and production maturity.
• Perform early prototyping by working with FPGA engineers.

Required Skills

• 5+ years of FPGA design experience using Verilog and SystemVerilog.
• 5+ years of experience with AMD/Xilinx FPGA design (7-series minimum; Kintex/Virtex UltraScale+ preferred).
• 4+ years of experience as a Digital Design Engineer or Chip Lead.
• Proficiency in RTL coding, synthesis, and SoC integration.
• Experience in digital design microarchitecture and ASIC architecture.
• Bachelor’s degree in Electrical/Computer Engineering or Computer Science.
• Experience with UPF-based simulation flows.
• SystemVerilog OVM/UVM experience.
• Scripting experience using TCL and Python.

Preferred Skills

• Experience with high-speed interfaces such as PCIe, USB, or MIPI.
• Knowledge of DFT/Testability requirements and test program definition.
• Experience with Power Aware GLS flow.

Key Skills

Education

Any Graduate