Description

You will focus on hardware verification and design validation using SystemVerilog and UVM.

Responsibilities

• Develop and maintain verification environments using SystemVerilog and UVM.
• Verify designs written in VHDL.
• Perform root-cause analysis on test failures.
• Collaborate with RTL designers to resolve verification issues.
• Manage source code using Git SCM with LFS and Submodules.

Required Skills

• 5+ years of experience writing SystemVerilog and UVM as a primary job function.
• Experience with VHDL design verification.
• Proficiency with Linux command line workflows.
• Experience writing TCL to control verification tools.
• Hands-on experience with Git SCM, including LFS and Submodules.
• Ability to perform root-cause analysis for test failures.
• Bachelor's degree.

Preferred Skills

• 10+ years of experience writing SystemVerilog and UVM.
• Proficiency in Perl or Python for text parsing and manipulation.
• Experience with Questa Sim, Visualizer, and DPI-based simulator interaction.
• Experience writing split Class/xRTL BFMs for simulation and Co-Emulation.
• Experience verifying designs for radiation-hardened Virtex FPGAs.

Key Skills

Education

Any Graduate