Description

You will own hardware verification and design validation for FPGA products.

This role is on-site.

Responsibilities

• Develop and maintain verification environments using SystemVerilog and UVM.
• Verify RTL designs written in VHDL.
• Perform root-cause analysis on test failures and collaborate with designers to resolve issues.
• Manage source code using Git SCM with LFS and Submodules.

Required Skills

• 5+ years of experience writing SystemVerilog and UVM as a primary job function.
• Experience with VHDL design verification.
• Proficiency with Linux command line workflows.
• Experience writing TCL to control verification tools.
• Hands-on experience with Git SCM, including LFS and Submodules.
• Bachelor's degree.

Preferred Skills

• 10+ years of experience writing SystemVerilog and UVM.
• Proficiency in Perl or Python for text parsing and manipulation.
• Experience with Questa Sim, Visualizer, and DPI-based simulator interaction.

Key Skills

Education

Any Graduate