Description

Key Skills: ASIC Verification, SystemVerilog, UVM, Coverage-Driven Verification, Testbench Development, Verilog, Regression Testing

Roles & Responsibilities:

• Perform system-level and block-level verification for ASIC designs.
• Develop verification plans and coverage strategies.
• Build and maintain UVM-based verification testbenches.
• Execute regression testing and achieve coverage closure.
• Develop verification infrastructure, stimulus, and scoreboarding components.
• Collaborate with RTL designers and architects to verify digital subsystems.
• Debug verification issues and improve verification methodologies.

Experience Required:

• 5-12 years of experience in ASIC verification.
• Strong expertise in SystemVerilog, UVM, and coverage-driven verification.
• Hands-on experience with testbench development and regression testing.
• Experience in verification planning, debugging, and coverage closure.
• Knowledge of Verilog and test case development is an added advantage.

Education: Any Graduation

Key Skills

Education

Any Graduate