Description

Own the verification of ASIC designs through system-level and block-level validation, testbench development, and coverage closure.

This role is on-site.

Responsibilities

• Develop verification plans and coverage strategies for digital subsystems.
• Build and maintain UVM-based verification testbenches and infrastructure.
• Execute regression testing and debug verification issues to ensure design correctness.
• Collaborate with RTL designers and architects to align on verification goals.
• Improve verification methodologies and achieve comprehensive coverage closure.

Required Skills

• 5-12 years of experience in ASIC verification.
• Strong expertise in SystemVerilog and UVM.
• Hands-on experience with coverage-driven verification and testbench development.
• Proficient in regression testing and debug methodologies.
• Knowledge of Verilog and test case development.

Preferred Skills

• Experience with verification planning and strategy formulation.

Key Skills

Education

Any Graduate