Description

Drive improvements in emulation technology and support methodology as part of the central team.

Responsibilities

• Develop emulation tools, workflows, and infrastructure to improve productivity across RTL, verification, validation, and SW teams.
• Support emulation methodology and tools including Veloce, Palladium, and ZeBu.
• Bring up and debug PCIe, DDR, and generic SOC interfaces.
• Integrate and bring up third-party accelerated verification IPs.
• Identify solutions for emulation challenges and implement ML/AI applications in emulation.

Required Skills

• 5+ years of experience in emulation-based verification using Cadence Palladium, Synopsys ZeBu, or Mentor Veloce.
• Proficiency in debugging complex SOC, GPU, or CPU core designs.
• Strong programming skills in C/C++, Verilog, SystemVerilog, and UVM.
• Experience with assembly and scripting in Perl or Python.
• Ability to triage regressions and resolve issues down to the RTL or testbench level.
• Experience developing and enhancing emulation transactors.

Preferred Skills

• Experience with UPF and power estimation-based emulation.

Key Skills

Education

ob Description: • Develop and drive improvements using the latest emulation technology from industry. • Support emulation methodology & emulations tools (Veloce, Palladium & ZeBu) as part of central methodology team. • Creating App Notes & Articles for Frequently Asked questions • Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW teams for productivity during debug, runtime, and data analysis of results from emulation runs. • Develop emulation validation components for validation efficiency in testing, debug and automation. • Bring up and debug PCIe, DDR and generic SOC interfaces. • Integrate and bring-up 3rd party accelerate verification IPs. • Identify solutions for emulation challenges and provide methodology. • Bring up ML/AI applications in emulation