Description

You will map multi-million gate SoC designs onto prototyping platforms and manage the full development lifecycle.

This role is on-site.

Responsibilities

• Map SoC designs onto prototyping platforms by creating design partitions, FPGA builds, and testbenches.
• Establish prototyping systems in the lab and evolve the existing prototyping methodology.
• Collaborate with Software, Design, and Verification teams to validate SoC functional and performance objectives.
• Triage, debug, and identify root causes of issues throughout all FPGA development phases.
• Engage in block-level RTL design or block and top-level IP integration as needed.

Required Skills

• Bachelor's Degree in Electrical or Computer Engineering with 10+ years of ASIC experience, or a Master's Degree with 8+ years of experience.
• Expertise in partitioning multi-million gate designs across multiple FPGAs.
• Proficiency in FPGA synthesis, place, and route flows.
• In-depth knowledge of digital design concepts including Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC).
• Experience with RTL coding using Verilog or SystemVerilog.
• Experience integrating third-party IPs.
• Scripting proficiency in TCL, Python, or Perl.

Preferred Skills

• Experience prototyping Networking SoCs on HAPS, Cadence Z2, or Zebu equivalent platforms.
• Understanding of PCIe, DDR, Ethernet, and Networking Protocols.
• Experience prototyping ARM or RISC-V CPUs.

Key Skills

Education

Bachelor's or Master's degrees