Description

You will design and develop digital logic for wireless communication systems and O-RAN architectures.

Responsibilities

• Design digital logic using Verilog or SystemVerilog.
• Implement DSP algorithms on FPGA hardware.
• Debug complex systems in the lab using Vivado ILAs, signal generators, and analyzers.
• Develop hardware models and test suites using C/C++ and Python.
• Integrate high-speed communication protocols into FPGA designs.

Required Skills

• 5-10 years of experience in FPGA design and development.
• Proficiency in Verilog and SystemVerilog.
• Experience with Xilinx Vivado and Intel Quartus.
• Knowledge of 4G/5G networks and O-RAN architectures.
• Practical experience with PCIe, Ethernet, JESD204B, and CPRI protocols.
• Strong understanding of DSP algorithms and FPGA implementation.
• Proficiency in C/C++ and Python for modeling and testing.
• Bachelor's or Master's degree in Computer Science, Computer/Electrical Engineering, Mathematics, or a related field.

Preferred Skills

• Experience with FPGA-based acceleration for AI/ML applications.
• Use of MATLAB/Simulink for DSP algorithm verification.
• Knowledge of power optimization, Linux device drivers, and embedded systems.

Key Skills

Education

Bachelor's or Master's degrees