Description

Key Requirements:

• 5+ years of experience in FPGA/ASIC Verification.
• Strong expertise in SystemVerilog and UVM.
• Hands-on experience in developing verification environments, testbenches, test cases, and coverage models.
• Experience with industry-standard EDA tools and verification methodologies.
• Strong knowledge of LPDDR and MIPI protocols, including protocol verification and debugging.
• Experience in simulation, regression, functional coverage, and verification closure.
• Good understanding of digital design and FPGA architectures.
• Familiarity with assertion-based verification and coverage-driven verification.
• Strong debugging and problem-solving skills.

Responsibilities:

• Develop and execute verification plans for FPGA-based designs.
• Build and maintain reusable UVM verification environments.
• Verify and validate designs involving LPDDR and MIPI interfaces.
• Perform functional verification, coverage analysis, and regression testing.
• Debug design and verification issues and work closely with design teams to drive closure.
• Ensure high-quality verification deliverables within project timelines

Key Skills

Education

Bachelor's degree