Description

You will own the verification and validation of FPGA-based designs, ensuring high-quality deliverables within project timelines.

This role is on-site.

Responsibilities

• Develop and execute verification plans for FPGA-based designs.
• Build and maintain reusable UVM verification environments, testbenches, and coverage models.
• Verify and validate designs involving LPDDR and MIPI interfaces.
• Perform functional verification, coverage analysis, and regression testing to drive verification closure.
• Debug design and verification issues and collaborate with design teams to resolve them.

Required Skills

• 5+ years of experience in FPGA or ASIC verification.
• Strong expertise in SystemVerilog and UVM methodologies.
• Hands-on experience developing verification environments, test cases, and coverage models.
• Strong knowledge of LPDDR and MIPI protocols, including protocol verification and debugging.
• Experience with industry-standard EDA tools and simulation frameworks.
• Good understanding of digital design and FPGA architectures.
• Familiarity with assertion-based verification and coverage-driven verification.

Preferred Skills

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.

Key Skills

Education

Bachelor's degree