Description

Design and integrate ASIC and FPGA digital architectures using RTL, managing timing analysis, closure, and verification processes.

This role is on-site.

Responsibilities

• Capture requirements and perform digital architecture design using RTL.
• Manage timing analysis, timing closure, and verification processes.
• Recommend new tools and practices to improve the ASIC/FPGA design flow.
• Lead project design teams by breaking down work, planning activities, and reporting status.

Required Skills

• 15+ years of experience in digital circuit architecture and design.
• RTL coding and simulation proficiency in VHDL and Verilog.
• Experience with resource tradeoffs and timing closure.
• Proficiency with simulation and synthesis tools such as ModelSim, Synplify, Quartus, or Vivado.
• Version control experience using Git or Subversion.
• Working knowledge of Unix environments.
• Scripting experience using C/C++ or Perl.

Preferred Skills

• Familiarity with chip-level verification using SystemVerilog, constrained random, or functional coverage.
• ASIC/FPGA lab validation using advanced lab equipment.

Key Skills

Education

Any Gradute