Description

You will design, develop, and debug RTL logic for FPGA-based hardware systems.

This role is on-site.

Responsibilities

• Design and implement RTL code using Verilog for protocols like PCIe, Ethernet, TCP/IP, and USB.
• Analyze and isolate RTL and test bench issues using simulation tools and UVM.
• Conduct hardware testing with logic analyzers, traffic analyzers, and test generators.
• Develop and maintain testbenches and simulation profiles in Linux and Windows environments.
• Optimize simulation efficiency and support HLS tooling processes.

Required Skills

• 2+ years of experience in RTL design and FPGA development.
• Proficiency in Verilog and UVM testbench methodologies.
• Experience with PCIe, Ethernet, TCP/IP, Packet processing, or USB protocols.
• Strong debugging skills using simulation tools.
• Proficiency in Perl, Python, Makefile, or shell scripting.
• Experience with C programming is an advantage.
• Ability to work with hardware test equipment.

Preferred Skills

• Experience with HLS tools and process.
• Background in customer-facing technical roles.

Key Skills

Education

Any Gradute