Description

You will own digital logic design and FPGA physical implementation, including floor-planning, place-and-route, and static timing analysis.

This role is hybrid.

Responsibilities

• Execute FPGA physical design flows for Xilinx and Intel devices.
• Implement and verify high-speed interfaces such as PCIe, AXI, DDRx, SERDES, USB, and 10/100GE.
• Write and review Verilog code, supported by Python, TCL, or PERL scripting.
• Utilize Cadence Xcellium, Synopsys Spyglass, Vivado, and Quartus for simulation and synthesis.
• Collaborate across teams to troubleshoot design issues and ensure signal integrity.

Required Skills

• 7+ years of practical hardware development experience.
• Expertise in Verilog and at least one scripting language (Python, TCL, or PERL).
• Strong understanding of digital logic design and FPGA physical design.
• Experience with Xilinx Vivado and Intel Quartus.
• Familiarity with Synopsys tools (Spyglass CDC/LINT) and Cadence Xcellium.
• Working knowledge of Windows and Linux environments.
• Bachelor’s degree in Electrical Engineering or related field.

Preferred Skills

• Standard cell ASIC design experience.
• Familiarity with System Verilog, UVM, VHDL, C, or C++.
• Experience with high-speed protocols like MIPI, DisplayPort, or HBM.

Key Skills

Education

Bachelor's degree