Description

Own the verification and validation lifecycle for FPGA-based hardware designs, ensuring quality through coverage-driven methodologies and DO-254 compliance.

This role is on-site.

Responsibilities

• Develop and maintain verification plans, executing activities and conducting reviews for FPGA designs.
• Build and debug verification environments using VHDL and SystemVerilog with UVM/UVMF, assertions, and coverage-driven techniques.
• Drive code coverage closure, assertion strategy, and verification quality metrics across simulation regressions.
• Coordinate simulation tools (QuestaSim, VCS, Aldec) to run complex verification suites and analyze results.
• Support hardware test setup and execution, ensuring alignment with DO-254 process requirements.

Required Skills

• 8+ years of relevant FPGA verification and validation experience.
• Expert-level VHDL and SystemVerilog verification using UVM/UVMF.
• Proficiency with simulation tools (QuestaSim, VCS, Aldec) and scripting for verification automation.
• Strong understanding of code coverage, assertions, and coverage-driven verification execution.
• B.E., B.Tech, or B.Tech M.Tech (Dual) in Electrical / Electronics / VLSI Design / VLSI Systems or related branches.

Preferred Skills

• DO-254 audits/certification experience and tool qualification.
• Experience with interface verification (PCIe, ARINC-429, MIL-1553, ARINC-818, SPI, AXI, ADC).
• MATLAB experience for algorithm development and stimulus generation.

Key Skills

Education

Any Graduate