Description

We are looking for a skilled FPGA Verification Engineer with strong experience in SystemVerilog and UVM-based verification to support advanced FPGA design, verification, and validation activities. The ideal candidate should have hands-on experience in developing verification environments, debugging complex issues, and ensuring high-quality FPGA designs.

 Key Skills:
• Strong experience in FPGA Verification and validation of complex digital designs
• Proficiency in SystemVerilog for developing testbenches and verification environments
• Experience working with UVM (Universal Verification Methodology) for scalable and reusable verification frameworks

 Tools:
• Hands-on experience with QuestaSim for simulation, debugging, and waveform analysis
• Familiarity with Synopsys VCS for running simulations and performing verification tasks

 Expertise:
• Experience in Code Coverage and Functional Coverage analysis to ensure verification completeness
• Strong debugging and problem-solving skills to identify and resolve design and verification issues
• Knowledge of modern verification methodologies and best practices for FPGA or ASIC verification

 Nice to Have:
• Experience with Python or Perl scripting for automation and verification flows
• Familiarity with Verilog or VHDL for understanding and working with RTL designs

 Education:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Key Skills

Education

Any Graduate