Description

You will develop and execute verification plans for FPGA designs.

Responsibilities

• Create and maintain test benches using industry-standard methodologies like UVM and SystemVerilog.
• Write and debug test cases to verify functionality, performance, and edge cases.
• Perform code and functional coverage analysis.
• Collaborate with design engineers to identify and resolve issues.
• Automate design tasks and write scripts to generate reports.

Required Skills

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in FPGA verification.
• Proficiency in SystemVerilog and UVM.
• Experience with verification tools such as QuestaSim and Synopsys VCS.
• Knowledge of code and functional coverage analysis.
• Experience with scripting languages, including Python and Perl.
• Familiarity with hardware description languages such as VHDL and Verilog.
• Strong debugging and problem-solving skills.

Key Skills

Education

Bachelor's or Master's degrees