Description

Lead LVS verification for complex full chip designs to ensure layout accuracy and specification compliance.

Responsibilities

• Develop and execute comprehensive LVS verification plans for full chip designs.
• Lead a team of engineers performing LVS checks and resolving layout-to-schematic discrepancies.
• Evaluate, select, and set up verification tools and flows including Cadence Assura, Mentor Calibre, and Synopsys IC Validator.
• Oversee debugging of LVS violations and collaborate with physical design and circuit teams to resolve root causes.
• Implement best practices, methodologies, and automation scripts to streamline verification processes.

Required Skills

• Several years of experience in LVS verification for complex full chip designs in a lead or senior role.
• Proficiency with industry-standard tools such as Cadence Assura, Mentor Calibre, or Synopsys IC Validator.
• Strong scripting skills in Tcl, Perl, or Python for developing automation.
• In-depth understanding of layout design principles and schematic representations.
• Proven ability to analyze complex LVS violations and lead cross-functional debugging efforts.
• Experience mentoring junior engineers and managing verification projects.
• Ability to maintain detailed documentation of verification plans, results, and debug reports.

Key Skills

Education

Any graduate