Description

You will focus on test-plan generation, creating, testing, and implementing verification plans.

Responsibilities

• Define, document, and implement UVM verification environments including agents and scoreboards.
• Write test plans and develop tests, test generators, test benches, checkers, and coverage.
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
• Support post-silicon verification activities in collaboration with design and product teams.

Required Skills

• 5+ years of experience with C/C++.
• 5+ years of experience with SystemVerilog.
• 5+ years of experience with UVM.
• Experience with pre and post-silicon verification test flows.
• Experience building automated test benches.
• Any Graduate degree.

Preferred Skills

• Experience with VMM or OVM.

Key Skills

Education

Any Gradaute