Description

You will manage the physical design process from Netlist to GDS, ensuring timing closure and physical verification across advanced technology nodes.

Responsibilities

• Drive physical design execution and methodologies to streamline workflows and produce technical guidelines.
• Collaborate with Front End teams to integrate physical design requirements early in the chip architecture phase.
• Resolve complex design and flow issues by identifying solutions and driving implementation.
• Perform floorplanning, clock tree synthesis, and ECO implementation to meet design targets.
• Debug LVS/DRC issues at both the chip and block levels using established verification methodologies.

Required Skills

• 8 to 12 years of experience in physical design and P&R.
• Hands-on experience with Netlist to GDS flows, including timing closure and physical verification.
• Proficiency with industry-standard tools such as Innovus, FirstEncounter, and ICC.
• Expertise in floorplanning, clock tree synthesis, and signal integrity.
• Experience performing IR drop analysis and ECO implementation.
• Practical knowledge of 28nm and 14nm technology nodes.
• Strong understanding of physical design verification to debug LVS/DRC issues.
• Bachelor's degree or equivalent hands-on work experience.

Key Skills

Education

Any Graduate