Description

You will work on physical design verification, focusing on block-level and full-chip automated PDV flows and scripts.

Responsibilities

• Perform physical verification checks including LVS, DRC, design-for-manufacturing, design-for-yield, and lithography at the chip and block level.
• Execute top-level tasks such as padring, bump placement, RDL design, floorplan, and integration.
• Collaborate with the packaging team on integration tasks.
• Execute SOC GDSII integration, seal ring addition, and generate tapeout collateral for foundry delivery.

Required Skills

• 5+ years of experience in hardware engineering or physical design verification.
• Proficiency with Innovus.
• Experience with LVS, DRC, and design-for-manufacturing.
• Knowledge of chip planning and seal ring implementation.
• Experience with physical verification tools such as Calibre and IC Validator.
• Competency in design-for-yield, lithography (LPC checks), and Electrical Rule Checks (ERC).
• Experience managing antenna effects and physical verification.

Preferred Skills

• Experience using Cadence Pegasus.

Key Skills

Education

ANY GRADUATE