Description

You will own physical design verification and SOC integration workflows, ensuring tapeout readiness for block-level and full-chip designs.

This role is remote.

Responsibilities

• Execute physical verification checks including LVS, DRC, design-for-manufacturing, and lithography at chip and block levels.
• Perform top-level integration tasks such as floorplan, padring, bump placement, RDL design, and seal ring addition.
• Generate tapeout collateral for foundry delivery and manage SOC GDSII integration.
• Collaborate with packaging teams on integration tasks and manage antenna effects.

Required Skills

• 5+ years of experience in hardware engineering or physical design verification.
• Proficiency with Cadence Innovus for implementation and planning.
• Experience with physical verification tools such as Calibre and IC Validator.
• Knowledge of LVS, DRC, and design-for-manufacturing methodologies.
• Competency in design-for-yield, lithography (LPC checks), and Electrical Rule Checks (ERC).
• Knowledge of chip planning and seal ring implementation.

Preferred Skills

• Experience using Cadence Pegasus.

Key Skills

Education

ANY GRADUATE