Description

You will focus on functional verification for IP blocks.

Responsibilities

• Develop and maintain tests for functional verification at the SOC level.
• Build testbench components to support next-generation IP.
• Maintain or improve current verification libraries for SOC/Full-chip verification.
• Provide technical support to cross-functional teams.
• Assist the Hardware emulation team in porting RTL to Palladium/Zebu or HAPS/Protium platforms.

Required Skills

• 4+ years of design verification experience.
• Proficiency in Verilog and Scripting.
• Experience with C and Perl programming languages.
• Familiarity with Python.
• Experience using Jiira.
• Background in Software Development.
• Education: BS/MS in EE, CE, or CS.

Key Skills

Education

Any Graduate