Description

You will own functional verification for IP blocks at the SOC level, building testbenches and maintaining verification libraries.

This role is on-site.

Responsibilities

• Develop and maintain tests for functional verification at the SOC level.
• Build testbench components to support next-generation IP.
• Maintain and improve current verification libraries for SOC and Full-chip verification.
• Provide technical support to cross-functional teams.
• Assist the Hardware emulation team in porting RTL to Palladium/Zebu or HAPS/Protium platforms.

Required Skills

• 4+ years of design verification experience.
• Proficiency in Verilog and scripting.
• Experience with C and Perl programming languages.
• Familiarity with Python.
• Experience using Jira.
• Background in Software Development.

Preferred Skills

• BS/MS in EE, CE, or CS.

Key Skills

Education

Any Graduate