Description

Key Skills: PCIe, UVM, SystemVerilog, ASIC Verification, IP Verification, DMA, CXL, Verilog, Linux, Perl

Good to Have Skills: Exposure to AI and LLMs in verification, HLS tools, simulation profiling, efficiency improvement, acceleration tools, Makefile scripting, shell scripting, leadership and mentorship experience, Windows environment experience.

Roles & Responsibilities:

• Collaborate with architects, hardware engineers, and firmware engineers to understand product requirements for FPGA and ASIC IP development.
• Build comprehensive test plan documentation for functionality, performance and product use cases to ensure high quality design verification.
• Develop UVM based testbench with support for directed and random test cases to achieve high quality design verification standards.
• Debug test failures, drive bug finding activities and coverage convergence to ensure zero bugs in final design implementation.
• Use AI technologies to drive efficiency and automation in verification processes and workflow optimization.
• Collaborate with partner verification and validation teams to provide comprehensive silicon debug support throughout the development lifecycle.

Experience Required: Proficient experience in IP level ASIC verification with strong knowledge of PCIe, CXL or other IO protocols. Experience with DMA verification, UVM testbenches, and working in Linux and Windows environments. Good understanding of UVM concepts and SystemVerilog language with hands-on experience in developing verification frameworks.

Education: Bachelors or Masters degree in Computer Engineering or Electrical Engineering

Key Skills

Education

Any Graduate